Sharing Knowledge. Fostering Collaboration.

The ICC brings the most eminent scholars and creative professionals in the field of computing to the campus
to exchange state-of-the-art research results and discuss future research directions.

Upcoming Lectures

Kalyan S. Perumalla
April 21, 2017

Distinguished Research and Development Staff Member and manager, Computer Science and Mathematics Division, Oak Ridge National Laboratory

Adjunct Professor, School of Computational Sciences and Engineering at Georgia Institute of Technology

Kalyan Perumalla is a Distinguished Research and Development Staff Member and manager in the Computer Science and Mathematics Division at the Oak Ridge National Laboratory, and an Adjunct Professor in the School of Computational Sciences and Engineering at the Georgia Institute of Technology. Dr. Perumalla founded and currently leads the Discrete Computing Systems Group at the Oak Ridge National Laboratory. In 2015, he was selected as a Fellow of the Institute of Advanced Study at the Durham University, UK. He was appointed to serve on the National Academies of Sciences Engineering and Medicine Technical Advisory Boards on Information Science and on Computational Sciences at the U.S. Army Research Laboratory, 2015-2017. Dr. Perumalla is among the first recipients of the U.S. Department of Energy Early Career Award in Advanced Scientific Computing Research, 2010-2015. Over the past 15 years, he has served as a principal investigator or co-principal investigator on research projects sponsored by the Department of Energy, Department of Homeland Security, Air Force, DARPA, Army Research Laboratory, National Science Foundation, and industry. Dr. Perumalla earned his Ph.D. in computer science from the Georgia Institute of Technology in 1999. His areas of interest include reversible computing, high performance computing, parallel discrete event simulation, and parallel combinatorial optimization. His notable research contributions are in the application of reversible computation to high performance computing and in advancing the vision of a new class of supercomputing applications using real-time, parallel discrete event simulations. High performance simulations spanning over 200,000 processor cores have been achieved by his algorithms and research prototypes on large supercomputing systems. He has published his research and delivered invited lectures and tutorials on topics spanning high performance computing and simulation. His recent book Introduction to Reversible Computing is among the first few in its area. He co-authored another book, three book chapters, and over 100 articles in peer-reviewed conferences and journals. Five of his co-authored papers received the best paper awards, in 1999, 2002, 2005, 2008, and 2014. Some of his research prototype tools in parallel and distributed computing have been disseminated to research institutions worldwide. Dr. Perumalla serves as program committee member and reviewer for international conferences and journals. He is a member of the editorial boards of the ACM Transactions on Modeling and Computer Simulation (TOMACS) and the SCS Transactions of the Society for Modeling and Simulation International (SIMULATION).
“Exascale computing,” being pursued by the US and others across the world, is the next level of supercomputing many times larger than the largest petascale parallel systems available today. Among the challenges in achieving exascale computing are the unprecedented levels of aggregate concurrency and the relatively low memory sizes per computational unit offered. Towards meeting these challenges, we present the design, development, and implementation of a novel technique called Cloning. Cloning efficiently simulates a tree of multiple what-if scenarios dynamically unraveled during the course of a base simulation. The lecture will describe the new conceptual cloning framework, and a prototype software system named CloneX that provides a new programming interface and implementation of cloning runtime scaled to supercomputing systems. CloneX efficiently and dynamically creates whole logical copies of what-if simulation trees across a large parallel system without the inordinate cost of full physical duplication of computation and memory. The approach is illustrated with example applications, including epidemilogical outbreaks and forest fire outbreaks, whose aggregate runtime and memory consumption using cloning are decreased by two to three orders of magnitude relative to replicated runs. Performance data on large simulation trees using 1024 GPUs reinforce the promise of cloning as an effective approach that can be adopted to meet the concurrency and memory challenges at exascale.

Lecture Archive, Spring 2017

Matt W. Mutka
March 28, 2017

Professor and Chairperson, Computer Science and Engineering, Michigan State University

Matt W. Mutka received the B.S. degree in electrical engineering from the University of Missouri-Rolla, the M.S. degree in electrical engineering from Stanford University, and the Ph.D. degree in Computer Sciences from the University of Wisconsin-Madison. He is on the faculty of the Department of Computer Science and Engineering at Michigan State University, where he is currently professor and chairperson. He has been a visiting scholar at the University of Helsinki, Helsinki, Finland, and a member of technical staff at Bell Laboratories in Denver, Colorado. He is an IEEE Fellow and was honored with the MSU Distinguished Faculty Award. His current research interests include mobile computing, sensor networking and wireless networking.
Accurate indoor position and movement information of devices enables numerous opportunities for location-based services. Services such as guiding users through buildings, highlighting nearby services, or tracking the number of steps taken are some of the opportunities available when devices compute accurate positioning information. GPS provides accurate localization results in an outdoor environment, such as navigation information for vehicles. Unfortunately, GPS cannot be applied indoors pervasively due to the various interferences. Although extensive research has been dedicated to this field, accurate indoor location information remains a challenge without the incorporation of expensive devices or sophisticated infrastructures within buildings. We explore some practical approaches for indoor map construction and indoor

Lecture Archive, Fall 2016

Zhiru Zhang
December 2, 2016

Assistant Professor, School of Electrical and Computer Engineering at Cornell University

Zhiru Zhang is an assistant professor in the School of ECE at Cornell University and a member of the Computer Systems Laboratory. His current research focuses on high-level design automation for heterogeneous computing. His work has been recognized with a best paper award from TODAES (2012), the Ross Freeman award for technical innovation from Xilinx (2012), an NSF CAREER award (2015), a DARPA Young Faculty Award (2015), the IEEE CEDA Ernest S. Kuh Early Career Award (2015). He co-founded AutoESL Design Technologies, Inc. to commercialize his PhD dissertation research on high-level synthesis. AutoESL was acquired by Xilinx in 2011 and the AutoESL tool was rebranded as Vivado HLS after the acquisition.

Systems across the computing spectrum, from handheld devices to warehouse-sized datacenters, are now power limited and increasingly turning to specialized hardware accelerators for improved performance and energy efficiency. Heterogeneous architectures integrating reconfigurable devices like FPGAs show significant potential in this role. However, there is still a considerable productivity gap between register-transfer-level FPGA design and traditional software design. Enabling high-level programming of FPGAs is a critical step in bridging this gap and pushing FPGAs further into the computing space.

In this talk, Zhiru will briefly review the progress he has made in research and commercialization on high-level synthesis (HLS) for FPGAs. In particular, he will use a few real-life applications as case studies to motivate the need for HLS tools, and explore their benefits and limitations. He will further describe novel synthesis algorithms that significantly improve the quality of the synthesized RTLs. Afterwards, he will outline major research challenges and introduce some of his ongoing work along those directions.

David Pan
October 7, 2016

Professor, Department of Electrical & Computer Engineering at The University of Texas at Austin

Engineering Foundation Endowed Professorship #1

David Z. Pan received his PhD degree in Computer Science from UCLA in 2000. He was a Research Staff Member at IBM T. J. Watson Research Center from 2000 to 2003. He is currently Engineering Foundation Professor at the Department of Electrical and Computer Engineering, University of Texas at Austin. He has published over 250 refereed journal/conference papers and 8 US patents, and graduated 20 PhD students. He has served in many journal editorial boards (TCAD, TVLSI, TCAD-I, TCAS-II, TODAES, Science China Information Science, etc.) and conference committees (DAC, ICCAD, DATE, ASPDAC, ISLPED, ISPD, etc.). He has received a number of awards, including the SRC Technical Excellence Award (2013), DAC Top 10 Author Award in Fifth Decade (2013), DAC Prolific Author Award (2013), ASP-DAC Frequently Cited Author Award (2015), 13 Best Paper Awards at premier venues, Communications of the ACM Research Highlights (2014), ACM/SIGDA Outstanding New Faculty Award (2005), NSF CAREER Award (2007), NSFC Overseas and Hong Kong/Macau Scholars Collaborative Research Award, SRC Inventor Recognition Award three times, IBM Faculty Award four times, UCLA Engineering Distinguished Young Alumnus Award (2009), UT Austin RAISE Faculty Excellence Award, many international CAD contest awards, among others. He is an IEEE Fellow.
As the semiconductor industry enters the era of extreme scaling (14nm, 11nm, and beyond), IC design and manufacturing challenges are exacerbated, due to the adoption of multiple patterning and other emerging lithography technologies. Meanwhile, new ways of “equivalent” scaling such as 2.5D/3D have gained tremendous interest and initial industry adoption, and new devices such as nanophotonics are making their headways to break the interconnect scaling bottleneck. Furthermore, hardware security has become a major concern due to fab outsourcing, extensive IP reuse, etc., thus unique identification/authentication and various IP protection schemes are in high demand. This talk will discuss some key challenges and recent results on bridging the design and technology gaps for manufacturability, reliability, and security for future ICs and integrated systems.

Kamau Bobb
October 4, 2016

NSF Program Officer in the Directorate for Computer & Information Science & Engineering

Research Scientist for Policy Analysis at CEISMC at Georgia Tech

Dr. Kamau Bobb is on assignment to the National Science Foundation where he is a Program Officer in the Directorate for Computer & Information Science & Engineering.  His portfolio includes CSforAll, INCLUDES, computing education, cyberlearning and broadening participation in STEM fields. At Georgia Tech he is a research scientist for Science and Technology Policy Analysis and one of the chief strategists for STEM education for the Georgia Tech Research Institute (GTRI). Prior to his current assignment he served as a liaison to the University System of Georgia (USG) and was the Director of the USG system-wide STEM Initiative.  Dr. Bobb has more than 10 years experience in STEM policy analysis and program implementation.  Prior to joining the faculty at Georgia Tech he was a science and technology policy analyst at SRI International where he conducted research on university strategic planning and STEM workforce analysis for clients in the United States and in the Middle East.  Dr. Bobb holds a Ph.D. in Science and Technology Policy from Georgia Tech and M.S. and B.S. degrees in Mechanical Engineering from the University of California Berkeley.

President Obama’s initiative, CS for All, is a call to the nation to improve computer science
instruction for all students. Against the backdrop of tremendous educational disparities,
the “for all” clause takes on particular importance. Dr. Bobb will outline the
role that the National Science Foundation is taking in this initiative. He will discuss the
nuanced challenges of equity in cs education and the hopeful prospects for the future on
this critical national initiative.

Keith Marzullo
September 15, 2016

Dean of the College of Information Studies (iSchool) at The University of Maryland

Former White House Office of Science and Technology Policy Director of Networking and Information Technology Research and Development (NITRD) Program

Former NSF Division Director for the Computer and Network Systems (CNS) Division in the Computer and Information Science and Engineering (CISE) Directorate

Dr. Keith Marzullo started on August 1, 2016 as the Dean of the College of Information Studies (also known as the iSchool) at the University of Maryland, College Park. He joined the iSchool from the White House Office of Science and Technology Policy, where he directed the Networking and Information Technology Research and Development (NITRD) Program. NITRD enables interagency coordination and cooperation among the over 20 member agencies which together spend over $4B a year in NIT R&D.

Dr. Marzullo joined NITRD from the National Science Foundation (NSF), where he served as the Division Director for the Computer and Network Systems (CNS) Division in the Computer & Information Science & Engineering (CISE) Directorate. He also served as Co-Chair of the NITRD Cybersecurity and Cyber Physical Systems R&D Senior Steering Groups.

Prior to joining NSF, Dr. Marzullo was a faculty member at the University of California, San Diego’s Computer Science and Engineering Department from 1993-2014, and served as the Department Chair from 2006-2010. He has also been on the faculty of the Computer Science Department of Cornell University (1986-1992) a Professor at Large of the Department of Informatics at the University of Tromsø (1999-2005), and was a principal in a startup (ISIS Distributed Systems, 1998-2002). Dr. Marzullo received his Ph.D. in Electrical Engineering from Stanford University, where he developed the Xerox Research Internet Clock Synchronization protocol, one of the first practical fault-tolerant protocols for keeping widely-distributed clocks synchronized with each other. His research interests are in distributed computing, fault-tolerant computing, cybersecurity, and privacy. Dr. Marzullo is also an ACM Fellow.

Computer science and engineering is undergoing explosive increases in enrollment, for which there are many theories and predictions. Computer science is also undergoing an explosive increase in another dimension: what is included in the domain. Dr. Marzullo will discuss this second explosive increase in the context of the President’s Council of Advisors on Science and Technology, and will examine some of the new areas that the Federal government has targeted. He will also speculate on how computer science and engineering departments might consider how to adapt to this situation.

Lecture Archive, Fall ’15 – Spring ’16

Amy Apon

Program Director, National Science Foundation
Professor and Chair of the Computer Science Division in the School of Computing, Clemson University

Dr. Amy Apon currently serves as a rotator to the National Science Foundation from Clemson University. A portion of the talk will include information about the NSF and NSF programs of interest to computer systems researchers.

At NSF, Apon is a Program Director in the Computer Systems Research (CSR), eXploiting Parallelism and Scalability (XPS), BigData, and Smart and Connected Health (SCH) programs. At Clemson University, Apon has held the position of Professor and Chair of the Computer Science Division in the School of Computing since 2011. As Chair, Apon has led the creation of a new program to grow the graduate enrollment, “CI SEEDS – Seeding the Next Generation Cyberinfrastructure Ecosystem” and has seen the number of publications and research expenditures more than double in the Division. Apon is co-Director of the Complex Systems, Analytics, and Visualization Institute (CSAVI), which includes the Big Data Systems and Analytics Lab. Her research focus includes performance modeling and analysis of parallel and distributed system, data-intensive computing in the application area of intelligent transportation systems, technologies for cluster computing, and the impact of high performance computing to research competiveness.

Apon was the elected Vice Chair and then Chair from 2009-2012 of the Coalition for Academic Scientific Computation, an organization of more than 70 leading U.S. academic institutions. Apon has led multiple successful collaborative NSF-funded projects that support high performance computing, including several awards from the NSF MRI program. Prior to joining Clemson, Apon was Professor at the University of Arkansas where she led the effort to develop the high performance computing capability for the State of Arkansas. The Arkansas High Performance Computing (HPC) Center was funded by the Arkansas Science and Technology Authority in May, 2008, and established under her direction. The acquisition of Red Diamond was the first computer in Arkansas ranked on the Top 500 list, in June 2005. The Arkansas Cyber-infrastructure Task Force Act was passed through her efforts in 2009. Dr. Apon has published over 100 peer-reviewed publications in areas of research, education, and impact of parallel and distributed computing.

The challenges of distributed and parallel data processing systems include heterogeneous network communication, a mix of storage, memory, and computing devices, and common failures of communication and devices. These complex computer systems of today are difficult, if not impossible, to model analytically. Experimentation using production-quality hardware and software and realistic data is required to understand system tradeoffs. At the same time, experimental evaluation has challenges, including access to hardware resources at scale, robust workload and data characterization, configuration management of software and systems, and sometimes insidious optimization issues around the mix of software stacks or hardware/software resource allocation. This talk presents a framework for experimental research in computer science, and examples and research challenges of experimentation as a tool in computer systems research within this framework.

Todd Austin

Professor of Electrical Engineering and Computer Science at the University of Michigan in Ann Arbor

Todd Austin is a Professor of Electrical Engineering and Computer Science at the University of Michigan in Ann Arbor. His research interests include computer architecture, robust and secure system design, hardware and software verification, and performance analysis tools and techniques. Currently Todd is director of C-FAR, the Center for Future Architectures Research, a multiuniversity SRC/DARPA funded center that is seeking technologies to scale the performance and efficiency of future computing systems. Prior to joining academia, Todd was a Senior Computer Architect in Intel’s Microcomputer Research Labs, a product-oriented research laboratory in Hillsboro, Oregon. Todd is the first to take credit (but the last to accept blame) for creating the SimpleScalar Tool Set, a popular collection of computer architecture performance analysis tools. Todd is co-author (with Andrew Tanenbaum) of the undergraduate computer architecture textbook, “Structured Computer Architecture, 6th Ed.”

In addition to his work in academia, Todd is founder and President of SimpleScalar LLC and co-founder of InTempo Design LLC.

In 2002, Todd was a Sloan Research Fellow, and in 2007 he received the ACM Maurice Wilkes Award for “innovative contributions in Computer Architecture including the SimpleScalar Toolkit and the DIVA and Razor architectures.”

Todd received his PhD in Computer Science from the University of Wisconsin in 1996.

Energy and power constraints have emerged as one of the greatest lingering challenges to progress in the computing industry. In this talk, I will highlight some of the “rules” of low-power design and show how they bind the creativity and productivity of architects and designers. I believe the best way to deal with these rules is to disregard them, through innovative design solutions that abandon traditional design methodologies. Releasing oneself from these ties is not as hard as one might think. To support my case, I will highlight two rule-breaking design technologies from my work. The first technique (Razor) combines low-power designs with resiliency mechanisms to craft highly introspective and efficient systems. The second technique (Subliminal) embraces subthreshold voltage design, which holds great promise for highly energy efficient systems.

Weisong Shi

Charles H. Gershenson Distinguished Faculty Fellow and a Professor of Computer Science at Wayne State University

Weisong Shi is a Charles H. Gershenson Distinguished Faculty Fellow and a Professor of Computer Science at Wayne State University. There he directs the Mobile and Internet SysTems Laboratory (MIST), Intel IoT Innovator Lab, and the Wayne Wireless Health Initiative, investigating performance, reliability, power- and energy-efficiency, trust and privacy issues of networked computer systems and applications.

Dr. Shi was on leave with the National Science Foundation as a Program Director in the Division of Computer and Network Systems, Directorate of Computer and Information Science and Engineering during 2013 – 2015, where he was responsible for the Computer and Network Systems (CNS) Core CSR Program, and two key crosscutting programs, including Cyber-Innovation for Sustainability Science and Engineering (CyberSEES), Smart and Connected Health (SCH). More information can be found at

Energy-efficiency is one of the most important design goals of today’s computing platforms, including both mobile devices at the edge of Internet and data centers in the cloud. In this talk, Dr. Shi will share his vision on energy-efficient computing, and their recent work toward this vision, including an energy efficient model for multicore systems, several tools for energy efficient software analysis and optimization, and workload-aware elastic customization techniques on servers. In the second part of the talk, Dr. Shi will share his experience on NSF proposal writing.

Yale Patt

Professor of ECE and the Ernest Cockrell, Jr. Centennial Chair in Engineering at The University of Texas at Austin

Yale N. Patt is Professor of ECE and the Ernest Cockrell, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He continues to thrive on teaching both the large (400+ students) freshman introductory course in computing and advanced graduate courses in microarchitecture, directing the research of eight PhD students, and consulting in the microprocessor industry. Some of his research ideas (e.g., HPS, the two-level branch predictor, ACMP) have ended up in the cutting-edge chips of Intel, AMD, etc. and some of his teaching ideas have resulted in his motivated bottom-up approach for introducing computing to serious students. The textbook for his unconventional approach, “Introduction to Computing Systems: from bits and gates to C and beyond,” co-authored with Prof. Sanjay Jeram Patel of University of Illinois (McGraw-Hill, 2nd ed. 2004), has been adopted by more than 100 universities world-wide. He has received the highest honors in his field for both his reasearch (the 1996 IEEE/ACM Eckert-Mauchly Award) and teaching (the 2000 ACM Karl V. Karlstrom Outstanding Educator Award). He was the inaugural recipient of the recently established IEEE Computer Society Bob Rau Award in 2011, and was named the 2013 recipient of the IEEE Harry Goode Award. He is a Fellow of both IEEE and ACM, and a member of the National Academy of Engineering. More detail can be found on his web page

After 50 years of teaching, I am convinced that the conventional method of introducing computing to all engineering students at most engineering schools is wrong, and that goes double for computer science and computer engineering majors. Teaching via a high level language (and worse yet an object-oriented course in JAVA) is a mistake and is almost guaranteed to ensure that the student will come away with little more than a superficial awareness of programming and practically no awareness of what the computer is doing. Two things I would like to do today: First, discuss why understanding computers is a core competency for engineering students of 2015 as much as physics and math are. Second, describe my approach, which I call “motivated bottom up,” and explain why I think it makes sense, how it affects the rest of the curriculum, and my experiences with it. I insist it is the correct introduction to computing to prepare students for doing any of the following three things in the future: (1) design a system that includes an embedded controller, whether that system be the gun director of a naval vessel, the cockpit controller of an airplane, or an automobile, (2) program a computer to solve some meaningful problem, or (3) design a computer system, either hardware or software or both for others to use.

The problem with the JAVA approach (or if you prefer, of the FORTRAN approach in the old days) is that students have no understanding of how a computer works and so they are forever memorizing patterns and hope that they can apply those patterns to the application at hand. Unfortunately, memorizing is not learning and the results have been as expected. I introduced the motivated bottom-up approach to the freshman class at Michigan in 1995, and have continually taught and refined it ever since. I start with the switch level behavior of a transistor and build from there. From transistors to gates to muxes, decoders, gated latches, finite state machines, memory, the LC-3 computer, machine language programming, assembly languge programming, and finally C programming. Students continue to build on what they already know, continually raising the level of abstraction. I have taught the course 13 times over the last 20 years to freshmen at Michigan and Texas, and an accelerated version of the course at USTC in Hefei and Zhejiang University in Hangzhou at the invitation of the Chinese.

The end of Moore’s Law we have been hearing about for 30 years. Another ten years and it will probably happen. What will that mean? More recently, there has been the suggestion that the days of the Von Neumann machine are numbered. In fact, we debated that notion at Micro in Cambridge last December, only to realize that most people predicting the demise of Von Neumann don’t even know what a Von Neumann machine is. Finally, we have already seen the end of Dennard Scaling and its influence on microprocessor design. But there is no vacuum when it comes to microprocessor hype. Dark silicon, quantum computers, approximate computing have all rushed in to fill the void. What I will try to do in this talk is examine each of these items from the standpoint of what they will mean for the microprocessor of the year 2025, and why the transformation hierarchy remains more critical than ever.